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1197 tm august 1997 features ? throughput rate . . . . . . . . . . . . . . . . . . . . . . . . . 160mhz ? resolution (HI20201). . . . . . . . . . . . . . . . . . . . . . . . 10-bit ? differential linearity error . . . . . . . . . . . . . . . . . . . 0.5 lsb ? low glitch noise ? analog multiplying function ? low power consumption . . . . . . . . . . . . . . . . . . . 420mw ? evaluation board available ? direct replacement for sony cx20201-1, cx20202-1 applications ? wireless communications ? signal reconstruction ? direct digital synthesis ? high definition video systems ? digital measurement systems ? radar description the HI20201 is a 160mhz ultra high speed d/a converter. the converter is based on an r/2r switched current source archi- tecture that includes an input data register with a complement feature and is emitter coupled logic (ecl) compatible. the HI20201 is available in a commercial temperature range and offered in a 28 lead plastic soic (300 mil) and a 28 lead plastic dip package. pinout HI20201 (pdip, soic) top view ordering information part number temp. range ( o c) package pkg. no. HI20201jcb -20 to 75 28 ld soic m28.3a-s HI20201jcp -20 to 75 28 ld pdip e28.6a-s HI20201-ev 25 evaluation kit (msb) d9 d8 d7 d6 d5 d4 d3 d2 d1 (lsb) d0 nc nc clk clk av ss av ee nc nc nc nc nc av ss dv ss compl dv ee v ref nc i out 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 fn3581.5 HI20201 10-bit, 160 msps, ultra high speed d/a converter caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
1198 typical application circuit functional block diagram d9 (msb) (1) d6 (4) d5 (5) d4 (6) d3 (7) d2 (8) d1 (9) d0 (lsb) (10) d9 d6 d5 d4 d3 d2 d1 d0 clk (14) 0.047 f (28) av ss (18, 19, 21-25) nc d/a out (20) i out 0.047 f 3.6k ? 1.0 f (26) av ee (27) v ref HI20201 d8 (2) d7 d7 (3) d8 digital data (ecl) clk (13) 82 ? 131 ? 131 ? -5.2v -1.3v clk 75 ? coax cable (15) dv ee (16) compl 1.0 f (17) dv ss 1.5k ? 1k ? tl431cp . -5.2v -5.2v 2k ? 82 ? (11) (12) ~ 2.7v upper 8-bit register clock buffer 6 lsbs current cells bias current generator v ref i out (lsb) d0 d1 d2 d3 d4 d5 d6 (msb) d9 compl clk clk d7 d8 input buffer 4-bit encoder 15 switched current cells r/2r net/work 15 15 15 15 15 15 15 15 HI20201
1199 absolute maximum ratings thermal information digital supply voltage dv ee to dv ss . . . . . . . . . . . . . . . . . . . -7.0v analog supply voltage av dd to av ss . . . . . . . . . . . . . . . . . . -7.0v digital input voltage . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 to dv ee v reference input voltage. . . . . . . . . . . . . . . . . . . . . . +0.3 to av ee v output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma thermal resistance (typical, note 1) ja ( o c/w) soic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s). . . . . . . . . . . . . 300 o c (soic - lead tips only) recommended operating conditions supply voltage av ee , dv ee . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75v to -5.45v av ee - dv ee . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05v to +0.05v digital input voltage v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to -0.7v v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.9v to -1.6v reference input voltage, v ref . . . . . . . v ee + 0.5v to v ee + 1.4v load resistance, r l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ? output voltage, v out . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8v to 1.2v temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -20 o c to 75 o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications t a = 25 o c, av ee = dv ee = -5.2v, agnd = dgnd = 0v, r l = , v out = -1v parameter test conditions HI20201jcb/jcp units min typ max system performance resolution 10 - - bits integral linearity error, inl f s = 160mhz (end point) - - 1.0 lsb differential linearity error, dnl f s = 160mhz - - 0.50 lsb offset error, v os (adjustable to zero) (note 3) - 7 - lsb full scale error, fse (adjustable to zero) (note 3) - - 102 lsb full scale output current, i fs --20ma dynamic characteristics throughput rate see figure 11 160 - - mhz glitch energy, ge r out = 75 ? -15-pv/s reference input voltage reference input range with respect to av ee +0.5 - +1.4 v reference input current v ref = -4.58v -0.1 -0.4 -3.0 a voltage reference to output small signal bandwidth -3db point 1v p-p input - 14.0 - mhz output rise time, t r r load = 75 ? -1.5- ns output fall time, t f r load = 75 ? -1.5- ns digital inputs input logic high voltage, v ih (note 2) -1.0 -0.89 v input logic low voltage, v il (note 2) -1.75 -1.6 v input logic current, i il , i ih (for d9 thru d6, compl) v ih = -0.89v, v il = -1.75v (note 2) 0.1 1.5 6.0 a input logic current, i il , i ih (for d5 thru d0) v ih = -0.89v, v il = -1.75v (note 2) 0.1 0.75 3.0 a timing characteristics data setup time, t su see figure 11 5 - - ns data hold time, t hld see figure 11 1 - - ns propagation delay time, t pd see figure 11 - 3.8 - ns settling time, t set (to 1 / 2 lsb) see figure 11 - 5.2 - ns HI20201
1200 timing diagram pin descriptions power supply characterisitics i ee -60 -75 -90 ma power dissipation 75 ? load - 420 470 mw notes: 2. parameter guaranteed by design or characterization and not production tested. 3. excludes error due to reference drift. 4. electrical specifications guaranteed only under the stated operating conditions. electrical specifications t a = 25 o c, av ee = dv ee = -5.2v, agnd = dgnd = 0v, r l = , v out = -1v (continued) parameter test conditions HI20201jcb/jcp units min typ max 28 pin soic pin name pin description 1-10 d0 (lsb)-d9 (msb) digital data bit 0, the least significant bit thru digital data bit 9, the most significant bit. 11, 12, 19, 21- 25 nc no connect, not used. 13 clk negative differential clock input. 14 clk positive differential clock input 15 dv ee digital (ecl) power supply -4.75v to -7v. 16 compl data complement pin. when set to a (ecl) logic high the input data is complemented in the input buffer. when cleared to a (ecl) logic low the input data is not complemented. 17 dv ss digital ground. 18 av ss analog ground. 20 i out current output pin. 26 av ee analog supply -4.75v to -7v. 27 v ref input reference voltage used to set the output full scale range. 28 av ss analog ground. clk clk data 0v d/a out -1v 90% 50% 10% n + 1 n + 1 n t su t hd t d n t r t f t d figure 1. ladder settling time full power bandwidth (ls) HI20201
1201 typical performance curves figure 2. v o(fs) ratio vs (v ref - v ee ) figure 3. full scale output voltage vs ambient temperature figure 4. output characteristics vs multiplying input signal frequency figure 5. glitch energy vs case temperature (full scale - 1023mv) v ref - v ee (v) 0.5 1.0 1.5 -2.0 -1.0 0 linear area r l = 10k ? r l = 75 ? t a = 25 o c, v ee = -5.2v full scale output voltage (v) 80 60 40 20 0 -20 ambient temperature ( o c) 1.05 1.00 0.95 r l = 75 ? r l = 10k ? full scale output voltage (relative value) v o(fs) /(v o(fs) at t a = 25 o c) 100k 10k 1m 10m 100m multiplying input signal frequency (hz) gain (db) 0 -10 -20 phase (degree) 0 -90 -180 gain phase -50 0 50 100 10.0 8.0 6.0 4.0 2.0 case temperature ( o c) glitch energy (pv/s) f clk = 100mhz HI20201
1202 detailed description the HI20201 is a 10-bit, current output d/a converter. the dac can run at 160mhz and is ecl compatible. the archi- tecture is segmented/r2r combination to reduce glitch and improve linearity. architecture the HI20201 is a combined r2r/segmented current source design. the 6 least significant bits of the converter are derived by a traditional r2r network to binary weight the 1ma current sources. the upper 4 most significant bits are implemented as segmented or thermometer encoded cur- rent sources. the encoder converts the incoming 4 bits to 15 control lines to enable the most significant current sources. the thermometer encoder will convert binary to individual control lines. see table 1. the architecture of the HI20201 is designed to minimize glitch while providing a manufacturable 10-bit design that does not require laser trimming to achieve good linearity. glitch glitch is caused by the time skew between bits of the incoming digital data. typically the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time (ttl designs). in an ecl system where the logic levels switch from one non-saturated level to another, the switching times can be considered close to symmetrical. this helps to reduce glitch in the d/a. unequal delay paths through the device can also cause one current source to change before another. to minimize this the inter- sil HI20201 employs an internal register, just prior to the cur- rent sources, that is updated on the clock edge. lastly the worst case glitch usually happens at the major transition i.e., 01 1111 1111 to 10 0000 0000. but in the HI20201 the glitch is moved to the 00 0001 1111 to 11 1110 0000 transition. this is achieved by the split r2r/segmented current source architecture. this decreases the amount of current switching at any one time and makes the glitch practically constant over the entire output range. by making the glitch a constant size over the entire output range this effectively integrates this error out of the end application. in measuring the output glitch of the HI20201 the output is terminated into a 75 ? load. the glitch is measured at the major carry?s throughout the dac?s output range. the glitch energy is calculated by measuring the area under the voltage-time curve. figure 7 shows the area considered as glitch when changing the dac output. units are typically specified in picovolt/seconds (pv/s). setting full scale the full scale output voltage is set by the voltage reference pin (27). the output voltage performance will vary as shown in figure 2. the output structure of the HI20201 can handle down to a 75 ? load effectively. to drive a 50 ? load figure 8 is sug- gested. note the equivalent output load is ~75 ? . table 1. thermometer encoder msb bit 8 bit 7 bit 6 thermometer code 1 = on, 0 = off, i 15 - i 0 0 0 0 0 000 0000 0000 0000 0 0 0 1 000 0000 0000 0001 0 0 1 0 000 0000 0000 0011 0 0 1 1 000 0000 0000 0111 0 1 0 0 000 0000 0000 1111 0 1 0 1 000 0000 0001 1111 0 1 1 0 000 0000 0011 1111 0 1 1 1 000 0000 0111 1111 1 0 0 0 000 0000 1111 1111 1 0 0 1 000 0001 1111 1111 1 0 1 0 000 0011 1111 1111 1 0 1 1 000 0111 1111 1111 1 1 0 0 000 1111 1111 1111 1 1 0 1 001 1111 1111 1111 1 1 1 0 011 1111 1111 1111 1 1 1 1 111 1111 1111 1111 (20) i out 34mhz low pass filter 75 ? 50 ? scope HI20201 figure 6. HI20201 glitch test circuit a (mv) t (ns) glitch energy = (a x t)/2 figure 7. glitch energy HI20201
1203 variable attenuator capability the HI20201 can be used in a multiplying mode with a variable frequency input on the v ref pin. in order for the part to operate correctly a dc bias must be applied and the incoming ac signal should be coupled to the v ref pin. see figure 13 for the application circuit. the user must first adjust the dc reference voltage. the incoming signal must be attenuated so as not to exceed the maximum (+1.4v) and minimum (+0.5v) reference input. the typical output small signal bandwidth is 14mhz. integral linearity the integral linearity is measured using the end point method. in the end point method the gain is adjusted. a line is then established from the zero point to the end point or full scale of the converter. all codes along the transfer curve must fall within an error band of 1 lsb of the line. fig- ure 10 shows the linearity test circuit. differential linearity the differential linearity is the difference from the ideal step. to guarantee monotonicity a maximum of 1 lsb differ- ential error is allowed. when more than 1 lsb is specified the converter is considered to be missing codes. figure 10 shows the linearity test circuit. clock phase relationship the HI20201 is designed to be operated at very high speed (i.e., 160mhz). the clock lines should be driven with ecl100k logic for full performance. any external data drivers and clock drivers should be terminated with 50 ? to minimize reflections and ringing. internal data register the HI20201 incorporates a data register as shown in the functional block diagram. this register is updated on the rising edge of the clk line. the state of the complement bit (compl) will determine the data coding. see table 2. thermal considerations the temperature coefficient of the full scale output voltage and zero offset voltage depend on the load resistance con- nected to i out . the larger the load resistor, the better (i.e., smaller) the temperature coefficient of the d/a. see figure 3 in the performance curves section. noise reduction digital switching noise must be minimized to guarantee system specifications. since 1 lsb corresponds to 1mv for 10-bit reso- lution, care must be taken in the layout of a circuit board. separate ground planes should be used for dv ss and av ss . they should be connected back at the power supply. separate power planes should be used for dv ee and av ee . they should be decoupled with a 1 f tantalum capacitor and a ceramic 0.047 f capacitor positioned as close to the body of the ic as possible. (18, 19, 21-25) nc d/a out (20) i out 39 ? 50 ? coax cable HI20201 100 ? figure 8. HI20201 driving a 50 ? load table 2. input coding table input code output code compl = 1 compl = 0 00 0000 0000 0 -1 10 0000 0000 -0.5 -0.5 11 1111 1111 -1 0 HI20201
1204 test circuits figure 9. current consumption, input current and output resistance 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b s1 a b s2 a b s3 a b s4 a b s5 a b s6 a b s7 a b s8 a b s9 a b s10 -0.89v or -1.75v a b s12 a s14 i 3 b a b s13 a s15 i 4 b -1.75v -0.89v ab s11 -1.75v -0.89v i 2 a b s20 a b i 6 a b s16 i 1 5.2v 4.56v a b s17 a s18 i 5 b 5.2v a b s19 v1 1ma HI20201
1205 figure 10. differential linearity error and linearity error test circuits (continued) d/a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 1.75v 0.89v 5.2v ? 5.2v v0 ?1? ?0? 10-bit data 1 shot clk 1.3v out 10k linearity errors are measured as follows s1 s2 s3 ? ? ? ? s9 s10 d/a out 0 0 0 ? ? ? ? 0 0 v 0 0 0 0 ? ? ? ? 0 1 v 1 0 0 0 ? ? ? ? 1 0 v 2 ? ? ? ? ? ? 1 1 1 ? ? ? ? 1 1 v 1023 integral linearity error differential linearity error v 0 v 1 v 1 - v 0 v 2 v 2 - v 1 v 4 v 4 - v 3 v 8 v 8 - v 7 v 16 v 16 - v 15 v 32 v 32 - v 31 v 64 v 64 - v 63 v 128 v 128 - v 127 v 192 v 192 - v 191 ? ? ? ? ? ? v 960 v 960 - v 959 v 1023 error at individual measurement points are calculated according to the following definition. (v 1023 - v 0 )/1023 = v 0(fs) /1023 1 lsb. ? adjust so that the full scale of dc voltage at pin 20 becomes 1.023v, that is, to satisfy v o - v 1023 = 1.023v. HI20201
1206 figure 11. maximum conversion rate, rise time, fall time, propagation delay, setup time, hold time and settling time circuit test circuits (continued) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dq q clkf -5.2v 131 82 82 131 -5.2v 1 / 6 hd100151 clkf a 82 131 82 131 -5.2v 1 131 470 131 82 1 dl 1 -1.3v -1.3v to pg 50 ? hd100116 b -5.2v c 39 100 to scope 50 ? -5.2v out clk clk lsb msb dl: delay line capacitors are 0.047 f ceramic chip capacitors unless otherwise specified. 10k ? HI20201
1207 measuring settling time settling time is measured as follows. the relationship between v and v 0(fs) as shown in the d/a output waveform in figure 12 is expressed as v = v 0(fs) (1 - e -t ). the settling time for respective accuracy of 10, 9 and 8-bit is specified as v = 0.9995 v 0(fs) v = 0.999 v 0(fs) v = 0.999 v 0(fs) which results in the following: t s = 7.60 for 10-bit, t s = 6.93 for 9-bit, and t s = 6.24 for 8-bit, rise time (t r ) and fall time (t f ) are defined as the time interval to slew from 10% to 90% of full scale voltage (v 0(fs) ): v = 0.1 v 0(fs) v = 0.9 v 0(fs) and calculated as t r = t f = 2.20 . the settling time is obtained by combining these expressions: t s = 3.45t r for 10-bit, t s = 3.15t r for 9-bit, and t s = 6.24t r for 8-bit figure 12. d/a output waveform figure 13a. test circuits (continued) v v 0(fs) = 1v 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a -5.2v to scope -5.2v clk clk b a gnd d gnd adjust so that the voltage at point b becomes -1v with no ac input. 10k ? 0.1 f 51 osc 0.047 ?1?
1208 figure 13b. figure 13c. figure 13. multiplying bandwidth test circuits (continued) waveform at point a v ee -0.62v v ee -0.31v waveform at point b -1v 1v p-p at 1mhz
1209 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 HI20201

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